A typical semiconductor memory device includes a plurality of memory cells or bitcells arranged in arrays, and a memory cell selector means for enabling the selection of a particular memory cell to facilitate the reading of data from, or the writing of data to, that particular memory cell.
For example, a high density dynamic random access memory (DRAM) includes a plurality of core cell blocks, and each core cell block contains several memory cells. The memory cells are metal-oxide semiconductor field-effect transistors (MOSFETs), and each MOSFET acts as a switch. To this end, each pair of MOSFETs is connected to a pair of bit lines (an input/output or I/O port), and the capacitance of each MOSFET can be charged by data. While one of the bit lines is the data itself, the other bit line is the complement data.
A bit line sense amplifier is provided in communication with a pair of bit lines corresponding to a set of memory cells. Each bit line sense amplifier amplifies the data which is read from the corresponding memory cell through the bit line pair or I/O port.
Before a typical read or write cycle, both bit lines of a memory cell are precharged. Then, during the data read or data write, the bit lines pass through a column decode (pass gates) and are routed to the bit line sense amplifier. When the inputs to the bit line sense amplifier trip, the data is known. After the inputs propagate through the bit line sense amplifier to the data output latch, the data read is complete, and the bit lines are again precharged to initiate the next data read or data write. As a result of waiting to again precharge the bit lines until the inputs have propagated through the bit line sense amplifier to the data output, the time to start the next memory operation (read or write) is not minimized.